Performance Analysis of Array Multiplier Using SPL and Control Input Technique Based Adder Cells for Neural Networks

In this article presents the investigation of array multipliers using SPL and control input technique based adder cells. The proposed SPL based adder cell consumes low power, small silicon area and low delay compared to control input technique based adder cell. The proposed circuit is tested with 4 bit array multiplier in terms of power, delay for 45 and 180 nm technology nodes. The array multiplier shows 20 % improvement in power consumption and 18% improvement in transistor count and these parameters are analyzed using cadence virtuoso software.